ECEA 5361 Hardware Description Languages for FPGA Design
2nd course in the FPGA Design for Embedded Systems Specialization
Instructors: Timothy Scherr, MSEE, Senior Instructor​ & Benjamin Spriggs, MBA, MSEE, Lecturer​
This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use them for design entry and verification with FPGAs and ASICs. You will use current HDL software tools for FPGA development, and practice with several programming examples that will give you proficiency with the languages. If you are thinking of a career in Electronics Design or looking at a career change, this is a great course to enhance your career opportunities.
Prior knowledge needed: ECEA 5360ÌýIntroduction to FPGA Design for Embedded Systems, knowledge of assembly and C Programming, Digital Logic Design, and basic computer architecture. Students should have a first course in each of these subjects. The corresponding CU-Boulder courses are ECEN 2120/2350, ECEN 3100/3350, and ECEN 1030/1310/CSCI 1300. To be specific, you are expected to be able to perform tasks similar to designing sequential circuits using Karnaugh maps or Boolean equations.
Syllabus
Duration: 8 hours
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers, and keywords. Finally, the use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
Duration: 12 hours
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers, and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are given ample opportunity to practice and refined their design techniques using the programming assignments.
Duration: 7Ìýhours
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators, and keywords. Finally, the use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
Duration: 10Ìýhours
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers, and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are given ample opportunity to practice and refined their design techniques by writing code as required by the programming assignments.
Duration: 2Ìýhours
This module contains materials for the proctored final exam for MS-EE degree students. If you've upgraded to the for-credit version of this course, please make sure you review the additional for-credit materials in the Introductory Module and anywhere else they may be found.
To learn about ProctorU's exam proctoring, system test links, and privacy policy, visitÌýwww.colorado.edu/ecee/online-masters/current-students/proctoru.
Grading
Assignment | Percentage of Grade |
| Week 1: VHDL Find the Code Errors Quiz | 2% |
| Week 1: Module 1 Quiz | 5% |
| Week 1 Programming Assignment: VHDL 2-bit Comparator | 2% |
| Week 1 Programming Assignment: VHDL Correct Errors | 2% |
| Week 1 Programming Assignment: VHDL Majority Vote | 2% |
| Week 1 Programming Assignment: VHDL 1-bit Full Adder | 2% |
| Week 2: Module 2 Quiz | 5% |
| Week 2 Programming Assignment: VHDL 74LS163 Binary Counter | 2% |
| Week 2 Programming Assignment: VHDL Make a Memory | 2% |
| Week 2 Programming Assignment: VHDL Finite State Machine | 2% |
| Week 2 Programming Assignment: VHDL ALU | 2% |
| Week 2 Programming Assignment: VHDL FIFO | 2% |
| Week 3: Verilog Find the Errors Quiz | 2% |
| Week 3: Module 3 Quiz | 5% |
| Week 3 Programming Assignment: Verilog 2-bit Comparator | 2% |
| Week 3 Programming Assignment: Verilog Correct Errors | 2% |
| Week 3 Programming Assignment: Verilog Majority Vote | 2% |
| Week 3 Programming Assignment: Verilog 1-bit Full Adder | 2% |
| Week 4: Module 4 Quiz | 5% |
| Week 4ÌýProgramming Assignment: Verilog 74LS163 Binary Counter | 2% |
| Week 4ÌýProgramming Assignment: Verilog Make a Memory | 2% |
| Week 4ÌýProgramming Assignment: Verilog Finite State Machine | 2% |
| Week 4ÌýProgramming Assignment: VerilogÌýALU | 2% |
| Week 4ÌýProgramming Assignment: Verilog FIFO | 2% |
| Week 5: ECEA 5361 Hardware Description Languages for FPGA Design Final Exam | 32% |
| Week 5: ECEA 5361 Final Exam Programming Assignment #1 | 4% |
| Week 5: ECEA 5361 Final Exam Programming Assignment #2 | 4% |
Letter Grade Rubric
Letter GradeÌý | Minimum Percentage |
| A | 92% |
| A- | 90% |
| B+ | 87% |
| B | 83% |
| B- | 80% |
| C+ | 77% |
| C | 73% |
| C- | 70% |
| D+ | 67% |
| D | 60% |
| F | 0% |
Component List
ÌýÌýNote: The DE10-Lite board is required for ECEA 5363 only.Ìý
Hardware (Required)
- Computer (able to run the required FPGA development tools)
- Operating systems:
- Windows 10 or 11
- Recent Linux OS (for example RHEL 6.5, CentOS 6.5 or later)
- Memory (RAM): at least 8 GB
- Disk Space: at least 20 GB free
Hardware (Recommended)
Bill of Materials (BOM)
Software
- Quartus Prime Lite Edition 16.1
- ModelSim Intel FPGA Edition 16.1
- Quartus Programmer and device support files (MAX 10 and Cyclone device families)
Course Syllabi
- ECEA 5360 Introduction to FPGA Design for Embedded Systems (0.8 credits)
- ECEA 5361 Hardware Description Languages for FPGA Design (0.8Ìýcredits)
- ECEA 5362 FPGA Softcore Processors and IP Acquisition (0.8 credits)
- ECEA 5363 Building FPGA Projects (0.6Ìýcredits)