ECEA 5363 FPGA Capstone: Building FPGA Projects

4th course in the FPGA Design for Embedded Systems Specialization

Instructor: Timothy Scherr, MSEE, Senior Instructor​

The objective of this course is provide a platform to get hands-on experience designing FPGA circuits and systems. To this end the DE10-Lite from TerAsic featuring the Intel Altera MAX10 FPGA is employed. The student will use this development kit to do a series of projects culminating in the construction of hardware and software for a System on a Chip (SoC) with the Nios II Soft Processor. All the prior lessons in this series of courses will be reinforced by the experience of building and testing real systems in the FPGA.

Prior knowledge needed: ECEA 5360ÌýIntroduction to FPGA Design for Embedded Systems,ÌýECEA 5361 Hardware Description Languages for FPGA Design,ÌýECEA 5362ÌýFPGA Softcore Processors and IP Acquisition

Learning Outcomes

  • Acquire an understanding of programmable systems on a chip for the purpose of creating prototypes or products for a variety of applications.
  • Understand the use and proper application of Soft Processors for FPGAs.
  • Create a Nios II Soft Processor, including both hardware and software design examples.
  • Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging.
  • Explore a number of example designs using FPGA development tools.

Syllabus

Duration: 10Ìýhours

In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA.

Duration: 8Ìýhours

The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument.

Duration: 8Ìýhours

The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit.

Duration: 5Ìýhours

The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well.Ìý

Duration: 2Ìýhours

Final Exam for this course.Ìý

To learn about ProctorU's exam proctoring, system test links, and privacy policy, visitÌýwww.colorado.edu/ecee/online-masters/current-students/proctoru.

Grading

Assignment
Percentage of Grade
Module 1 Peer Review5%
Module 1 Project Programming Assignment10%
Module 1 Quiz5%
Module 2 Peer Review5%
Module 2 Project Programming Assignment10%
Module 2 Quiz5%
Module 3ÌýPeer Review5%
Module 3ÌýProject Programming Assignment10%
Module 3ÌýQuiz5%
Module 4ÌýPeer Review5%
Module 4ÌýProject Programming Assignment10%
Module 4ÌýQuiz5%
ECEA 5363 FPGA Capstone: Building FPGA Projects Final Exam20%

Letter Grade Rubric

Letter GradeÌý
Minimum Percentage
A92%
A-90%
B+87%
B83%
B-80%
C+77%
C73%
C-70%
D+67%
D60%
F0%

Component List

ÌýÌýNote: The DE10-Lite board is required for ECEA 5363 only.Ìý

Hardware (Required)
  • Computer (able to run the required FPGA development tools)
  • Operating systems:
    • Windows 10 or 11
    • Recent Linux OS (for example RHEL 6.5, CentOS 6.5 or later)
  • Memory (RAM): at least 8 GB
  • Disk Space: at least 20 GB free
Hardware (Recommended)
Bill of Materials (BOM)
Software
  • Quartus Prime Lite Edition 16.1
  • ModelSim Intel FPGA Edition 16.1
  • Quartus Programmer and device support files (MAX 10 and Cyclone device families)
Course Syllabi